Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device, in forming plugs, an alignment error margin between wirings and lower plugs is increased by using a conductive pad and thus avoids an increase of a contact resistance caused by an alignment error and improves reliability.

Claims

1 . A method for manufacturing a semiconductor device including the steps of: providing a semiconductor substrate on which a cell region and an peripheral circuit region are separately formed, and a plurality of junction regions are formed; forming a first interlayer insulating film on the semiconductor substrate; forming a first contact hole on a first junction region selected from the plurality of junction regions by etching a predetermined region of the first interlayer insulating film; forming a first contact plug on the inside of the first contact hole; forming a conductive pad having wider area than the first contact plug over the first contact plug; forming a second interlayer insulating film on the whole structure including the conductive pad; etching a predetermined region of the first and second interlayer insulating films such that the second contact hole is formed over a second junction region among the plurality of junction regions and on the second conductive pad; and forming a second contact plug in the second contact hole. 2 . A method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming the conductive pad includes: forming a third interlayer insulating film on the whole structure including the first contact plug; etching the third interlayer insulating film over the first contact plug; and filling conductive material into an area where the third interlayer insulating film is removed. 3 . A method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming the conductive pad further includes a step of forming a dummy conductive pad on a region where the first contact plug is not formed. 4 . A method for manufacturing a semiconductor device according to claim 1 , further including a step of forming metal wiring on the second contact plug, after forming the second contact plug. 5 . A method for manufacturing a semiconductor device according to claim 1 , wherein the first junction region includes a source junction region and a well pick up region on the cell region, and a junction region on the peripheral circuit region, and the second junction region includes a drain junction region on the cell region. 6 . A method for manufacturing a semiconductor device according to claim 1 , comprising a step, before forming the first interlayer insulating film, of further forming a drain select line, a plurality of memory cell gates, and a source select line on the cell region of the semiconductor substrate, and further forms a transistor gate on the peripheral circuit region of the semiconductor substrate. 7 . A method for manufacturing a semiconductor device according to claim 1 , comprising forming the first interlayer insulating film in a thickness of 5000 Å-10000 Å by using high density plasma (HDP) oxidation film. 8 . A method for manufacturing a semiconductor device according to claim 1 , comprising forming the second interlayer insulating film in a thickness of 1000 Å-5000 Å by using a high density plasma (HDP) oxidation film or a PE-TEOS (Plasma Enhanced Tetra Ethyl OrthoSilicate) oxidation film. 9 . A method for manufacturing a semiconductor device according to claim 2 , comprising forming the third interlayer insulating film in a thickness of 1000 Å-5000 Å by using a high density plasma (HDP) oxidation film or a PE-TEOS (Plasma Enhanced Tetra Ethyl OrthoSilicate) oxidation film. 10 . A method for manufacturing a semiconductor device according to claim 1 , comprising performing the etching processes of the first interlayer insulating film and second interlayer insulating film with a selection ratio of 5:1-20:1, at a pressure of 15 mTorr-40 mTorr, a temperature of 20° C.-40° C. and a bottom power of 1000 W-1500 W, and, using at least one member selected from the group consisting of CF 4 , C x H y F z , where x is 1 to 5, y is 0 to 3, and z is 1 to 8, Ar, and O 2 as an etchant. 11 . A method for manufacturing a semiconductor device according to claim 2 , comprising performing the etching process of the third interlayer insulating film with a selection ratio of 5:1-20:1, at a pressure of 15 mTorr-40 mTorr, a temperature of 20° C.-40° C. and a bottom power of 1000 W-1500 W, and using at least one member selected from the group consisting of CF 4 , C x H y F z , where x is 1 to 5, y is 0 to 3, and z is 1 to 8, Ar, and O 2 as an etchant. 12 . A method for manufacturing a semiconductor device according to claim 1 , wherein the conductive pad is formed of metal or polysilicon.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The invention relates to a method for manufacturing a semiconductor device and more particularly, to a method for manufacturing a semiconductor device by which an alignment error margin between a wiring and a plug formed thereunder can be increased. [0003] 2. Related Technology [0004] FIGS. 1A to 1D are sectional views showing subsequently a method for manufacturing a semiconductor device according to the prior art. [0005] Referring to FIG. 1A , through a conventional process, a drain select line 21 d , a plurality of cell gates 21 c , and a source select line 21 s are formed on a cell region of the semiconductor substrate 20 , and junction regions 20 a to 20 c are formed, respectively, therebetween. In addition, a junction region (not shown) is formed between the cell gates 21 c . Meanwhile, a transistor gate 21 g and junction regions 20 d , 20 e are formed on a peripheral circuit region. In addition, on the whole structure, a first interlayer insulating film 22 is formed and a source contact plug 23 is formed on the junction region 20 b where the first interlayer insulating film 22 is etched. Again, a second interlayer insulating film 24 is formed on the whole structure including the source contact plug 23 , and a first hard mask that exposes a drain contact plug 26 a on the cell region and a contact plug region 26 b on the peripheral circuit region, is formed over the second interlayer insulating film 24 . [0006] Referring to FIG. 1B , the lower second interlayer insulating film 24 and first interlayer insulating film 22 are etched subsequently by using the first hard mask 24 (see FIG. 1 ) as an etching mask such that the junction regions 20 a , 20 e on the cell region and peripheral circuit region are exposed. In addition, the conductive material such as metal or polysilicon, etc., is filled into the space where the first and second interlayer insulating films 22 , 24 are removed, to simultaneously form the drain contact plug 27 a on the cell region and the contact plug 27 b on the peripheral circuit region. [0007] Then, the hard mask 25 (see FIG. 1 ) is removed to subsequently form a third interlayer insulating film 28 and a second hard mask 29 . In addition, the predetermined region of the third interlayer insulating film 28 is etched by using the second hard mask 29 as an etching mask to form a bit line trench 30 a , a source trench 30 b , and a well pick up trench 30 c on the cell region, and a trench 30 e that exposes the well pick up trench 30 d and contact plug 27 b on the peripheral circuit region. [0008] Referring to FIG. 1C , a photoresist pattern 31 is formed on the upper part of the whole structure including the second hard mask 29 and the predetermined regions of the second interlayer insulating film 24 and first interlayer insulating film 22 are subsequently etched by an etching process using the photoresist pattern 31 as an etching mask. As a result, a source pick up contact hole 32 a and a well pick up contact hole 32 b , which expose the source contact plug 23 , are formed on the cell region and a well pick up contact hole 32 c that exposes the junction region 20 d is formed on the peripheral circuit region. [0009] Referring to FIG. 1D , the photoresist pattern 31 (see FIG. 1C ) and second hard mask 29 (see FIG. 1C ) are removed and then conductive material is filled into the trench and the contact hole to form a wiring for a bit line 33 a , a wiring for a source line 33 b , wirings for well pick up 33 c , 33 d and a metal wiring 33 e. [0010] Here, since the widths of the plugs that are formed in the manner described above are significantly narrow, an alignment margin with the wirings that are formed on the plugs in the following processes is very important. In particular, in the case where the bit line has a single page buffer, since it has more bit line page buffer patterns, the alignment margin between the wirings and lower plugs is further decreased such that resistance may be increased or failure may be caused due to an alignment error. SUMMARY OF THE INVENTION [0011] The invention has been proposed to solve the above drawbacks, and relates to increasing an alignment between wirings and lower plugs by using a conductive pad in forming plugs and thus avoid an increase of a contact resistance caused by an alignment error. [0012] A method for manufacturing a semiconductor device according to the invention may include the steps of providing a semiconductor substrate on which a cell region and a peripheral circuit region are separately formed, and a plurality junction regions are formed, forming a first interlayer insulating film on the semiconductor substrate, forming a first contact hole on a first junction region among the plurality of junction regions by etching a predetermined region of the first interlayer insulating film, forming a first contact plug on the inside of the first contact hole, forming a conductive pad having wider area than the first contact plug over the first contact plug, forming a second interlayer insulating film on the whole structure including the conductive pad, etching a predetermined region of the first and second interlayer insulating film such that the second contact hole is formed over a second junction region among the plurality of junction regions and on the second conductive pad, and forming a second contact plug in the second contact hole. [0013] The step of forming the conductive pad preferably includes forming a third interlayer insulating film on the whole structure including the first contact plug, etching the third interlayer insulating film over the first contact plug, and filling conductive material into the part where the third interlayer insulating film is removed. [0014] The step of forming the conductive pad preferably includes a step of forming a dummy conductive pad on a region where the first contact plug is not formed. [0015] In one embodiment, a method for manufacturing a semiconductor device according to the invention may further include a step of forming metal wiring on the second contact plug, after forming the second contact plug. [0016] The first junction region preferably includes a source junction region and a well pick up region on the cell region, and a junction region on the peripheral circuit region, and the second junction region preferably includes a drain junction region on the cell region. [0017] Before forming the first interlayer insulating film, a drain select line, a plurality of memory cell gates, and a source select line are preferably further formed on the cell region of the semiconductor substrate, and a transistor gate is preferably further formed on the peripheral circuit region of the semiconductor substrate. [0018] The first interlayer insulating film is preferably formed in a thickness of 5000 Å-10000 Å by using HDP oxidation film, and the second interlayer insulating film and third interlayer insulating film to preferably formed in a thickness of 1000 Å-5000 Å by using a HDP oxidation film or PE-TEOS (Plasma Enhanced Tetra Ethyl OrthoSilicate) oxidation film. [0019] The etching processes of the first to third interlayer insulating films are preferably performed with a selection ratio of 5:1-20:1, at a pressure of 15 mTorr-40 mTorr, a temperature of 20° C.-40° C. and a bottom power of 1000 W-1500 W, and one or more of CF 4 , C x H y F z , where x is 1 to 5, y is 0 to 3, and z is 1 to 8, Ar, and O 2 is preferably used as an etchant. [0020] The conductive pad is preferably formed of metal or polysilicon. BRIEF DESCRIPTION OF THE DRAWINGS [0021] The following drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. [0022] FIGS. 1A to 1D are sectional views showing subsequently a method for manufacturing a semiconductor device according to the prior art; and [0023] FIGS. 2A to 2D are sectional views showing subsequently a method for manufacturing a semiconductor device according to the invention. DESCRIPTION OF SPECIFIC EMBODIMENTS [0024] In the following, preferred embodiments of the invention will be described in conjunction with the accompanying drawings. However, both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed. [0025] FIGS. 2A to 2D are sectional views showing a method for manufacturing a semiconductor device according to the invention. [0026] Referring to FIG. 2A , through any suitable process, a drain select line 51 d , a plurality of memory cell gates 51 c , and a source select line 51 s are formed on a cell region of the semiconductor substrate 50 , and a drain region 50 a , a source region 50 b , and a well pick up region 50 c are formed, respectively, therebetween. In addition, a junction region (not shown) is formed between the cell gates 51 c . Meanwhile, a transistor gate 51 g and a junction region 50 d are formed on an peripheral circuit region. In addition, on the whole structure, a first interlayer insulating film 52 is formed. Then, the interlayer insulating film 52 under which the source region 50 b and well pick up region 50 c are disposed on the cell region, and the junction region 50 d is disposed on the peripheral circuit region, is selectively etched to form, respectively, a first source contact plug 53 a , a first well pick up plug 53 b and a first contact plug 53 c . Here, the first source contact plug 53 a is formed as a line form. [0027] In conjunction with the configurations of the aforementioned elements, the first interlayer insulating film 52 may be formed of arbitrary material having dielectric characteristics; however, preferably, it may formed of an HDP oxidation film of 5000 Å-10000 Å. In addition, in etching the first interlayer insulating film 52 , the etching process may preferably be performed with a selection ratio of 5:1-20:1, at a pressure of 15 mTorr-40 mTorr, a temperature of 20° C.-40° C. and a bottom power of 1000 W-1500 W. At this time, one or more of CF 4 , C x H y F z , where x is 1 to 5, y is 0 to 3, and z is 1 to 8, Ar, and O 2 is preferably used as an etchant. C x H y F z , may be, for example, CF 4 , C 4 F 6 , CH 2 F 2 , C 3 F 8 , CHF 3 , C 4 F 8 , C 5 F 6 , C 2 F 6 , CH 3 F, etc. [0028] Referring to FIG. 2B , a second interlayer insulating film 54 is formed over the aforementioned structure. In addition, the second interlayer insulating film 54 over the plugs 53 a to 53 c is selectively etched. As a result, the plugs 53 a to 53 c formed over the semiconductor substrate 50 are exposed. At this time, to expose the first interlayer insulating film adjacent to the plugs 53 a to 53 c , the areas of the second interlayer insulating film 54 that are wider than the upper surface areas of the plugs 53 a to 53 c , are removed. Then, conductive material is filled into the part where the second interlayer insulating film is removed. [0029] As the conductive material, conventional material used in a semiconductor process may be used, and preferably metal such as tungsten or polysilicon, etc., is used. As a result, contact pick up pads 55 b , 55 d and a well pick up pad 55 c (see FIG. 2 c ) are formed over the plugs 53 a to 53 c , respectively, and these pads 55 b to 55 d are electrically connected to the plugs 53 a to 53 c formed thereunder. In addition, in such region where a plug is not formed as the region where the cell gate 51 c is formed, a dummy pad 55 a may be formed. The dummy pad 55 a functions as an etching-interference film in the following process and avoids an excessive etching of the lower layer. [0030] In conjunction with the configurations of the aforementioned elements, the pads 55 b to 55 d function to increase the upper surface of the plugs 53 a to 53 c formed thereunder. Accordingly, the contact area with contact plugs or metal wirings to be formed in later is increased and thus a alignment margin is increased, thereby avoiding an increase of a resistance or a failure, caused by an alignment error. [0031] In conjunction with the configurations of the aforementioned elements, the second interlayer insulating film 54 may be formed of any suitable material having dielectric characteristics; however, preferably, it may formed of an HDP oxidation film or PE-TEOS (Plasma Enhanced Tetra Ethyl OrthoSilicate) of 1000 Å-5000 Å. In addition, in etching the second interlayer insulating film 54 , the etching process is preferably performed with a selection ratio of 5:1-20:1, at a pressure of 15 mTorr-40 mTorr, a temperature of 20° C.-40° C. and a bottom power of 1000 W-1500 W. At this time, one or more of CF 4 , C x H y F z , where x is 1 to 5, y is 0 to 3, and z is 1 to 8, Ar, and O 2 is preferably used as an etchant. [0032] Referring to FIG. 2C , a third interlayer insulating film 56 is formed over the whole structure including the pads 55 b to 55 d . Then, the predetermined region of the third interlayer insulating film 56 , second interlayer insulating film 54 and first interlayer insulating film 52 over the drain region 50 a , source region 50 b , well pick up region 50 c , and junction region 50 d , is etched. At this time, in the region where the pads 55 b to 55 d are not formed, all of the third interlayer insulating film 56 , second interlayer insulating film 54 and first interlayer insulating film 52 are etched to expose the drain region 50 a . However, over the source region 50 b , well pick up region 50 c , and junction region 50 d , the second interlayer insulating film 54 and first interlayer insulating film 52 are not etched with the pads 55 b to 55 d , and only the third interlayer insulating film 56 is etched to expose a region of the pads 55 b to 55 d . As a result, a drain contact hole is formed over the drain region 50 a and a source contact hole is formed on the pad 55 b over the well pick up region 50 c , and a contact hole is formed on the pad 55 d over the junction region 50 d . In a subsequent step, conductive material is filled into the insides of these holes to form a drain contact hole 57 a , a second source contact hole 57 b , a second well pick up hole 57 c , and a second contact plug 57 d . Then, a fourth interlayer insulating film 58 is formed on whole structure. [0033] In conjunction with the configurations of the aforementioned elements, the third interlayer insulating film 56 is preferably formed of arbitrary material having dielectric characteristics; however, preferably, it may formed of an HDP oxidation film or PE-TEOS (Plasma Enhanced Tetra Ethyl OrthoSilicate) of 1000 Å-5000 Å. In addition, in etching the second interlayer insulating film 56 , the etching process may be preferably performed with a selection ratio of 5:1-20:1, at a pressure of 15 mTorr-40 mTorr, a temperature of 20° C.-40° C. and a bottom power of 1000 W-1500 W. At this time, one or more of CF 4 , C x H y F z , where x is 1 to 5, y is 0 to 3, and z is 1 to 8, Ar, and O 2 is preferably used as an etchant. [0034] Referring to FIG. 2D , the fourth interlayer insulating film 58 over the drain contact plug 57 a , second source contact plug 57 b , second well pick up plug 57 c and second contact plug 57 d , is selectively etched. As a result, the plugs 57 a to 57 d are exposed. Then, conductive material is filled into the etched-region of the fourth interlayer insulating film 58 to form the wiring 59 . [0035] According to the invention, in forming plugs, an alignment error margin between wirings and lower plugs is increased by using a conductive pad and thus at an increase of a contact resistance caused by an alignment error is provided and reliability is improved.

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