A Current Mirror with Circuitry That Allows for Over Voltage Stress Testing

Abstract

A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and the drain of the first transistor; a bias source coupled to a control node of the switch such that the switch is ON during normal current mirror operation, and the switch is OFF during over voltage stress testing; and a clamp coupled between the control node of the switch and a source node.

Claims

1 . A current mirror circuit that allows for over voltage stress testing comprising: a first PMOS transistor; a second PMOS transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and a drain of the first transistor; a bias source coupled to a control node of the switch; and a clamp coupled between the control node of the switch and a source node. 2 . The circuit of claim 1 further comprising: a third transistor coupled in series with the first transistor; and a fourth transistor coupled in series with the third transistor. 3 . (canceled) 4 . The circuit of claim 2 wherein the third and fourth transistors are NMOS transistors. 5 . The circuit of claim 1 wherein the switch is a transistor. 6 . The circuit of claim 1 wherein the switch is a PMOS transistor. 7 . The circuit of claim 1 wherein the bias source comprises a transistor. 8 . The circuit of claim 1 wherein the bias source comprises an NMOS transistor. 9 . The circuit of claim 1 wherein the clamp comprises diodes. 10 . (canceled)
FIELD OF THE INVENTION [0001] The present invention relates to electronic circuitry and, in particular, to a current mirror with circuitry that allows for over voltage stress testing. BACKGROUND OF THE INVENTION [0002] To perform an over voltage stress test (OVST) on a high-side PMOS in a current mirror configuration, the gate of the PMOS device must be raised to a high voltage using a probe pad and the current into the gate of the device must be measured. To accurately measure gate current, the DC current into all other components connected to the gate node must be very low (ideally zero). The two-fold problem is that all components connected to the gate node must be able to withstand a high DC voltage and must not provide any current paths from the node. [0003] A basic prior art PMOS current mirror is shown in FIG. 1 . The circuit of FIG. 1 includes PMOS transistors Mp 2 and Mp 3 ; NMOS transistors Mn 3 and Mn 1 ; voltage nodes Vgp, Vdd, Vout, Vcc 3 , and Von; and output current Iout. When considering the basic prior art PMOS current mirror, as shown in FIG. 1 , the problem specifically is when the voltage on node Vgp is raised above node Vdd. In this case, the parasitic diode from the drain to the well of device Mp 2 is activated, providing a significant current path from node Vgp to source node Vdd and making OVST impossible. SUMMARY OF THE INVENTION [0004] A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and the drain of the first transistor; a bias source coupled to a control node of the switch such that the switch is ON during normal current mirror operation, and the switch is OFF during over voltage stress testing; and a clamp coupled between the control node of the switch and a source node. BRIEF DESCRIPTION OF THE DRAWINGS [0005] In the drawings: [0006] FIG. 1 is a circuit diagram of a basic prior art current mirror; [0007] FIG. 2 is a circuit diagram of a preferred embodiment current mirror circuit with over voltage stress testing capability. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0008] The preferred embodiment current mirror circuit with over voltage stress testing capability, shown in FIG. 2 , introduces a switch Mp 1 between the drain and gate of device Mp 2 . The circuit of FIG. 2 includes the elements of the circuit of FIG. 1 , and additionally includes diodes D 1 , D 2 , and D 3 ; NMOS transistor Mn 2 ; and voltage node Vb 10 u . The well and source of switch Mp 1 are connected to node Vgp to prevent activation of any parasitic components during over voltage stress testing (OVST). The gate of switch Mp 1 is biased to remain on during normal operation by transistor Mn 2 and bias voltage node Vb 10 u . In addition, a clamp to source node Vdd (diodes D 1 , D 2 , and D 3 ) is used to limit the maximum gate-to-source voltage of the switch Mp 1 . Device Mn 2 is biased to provide a low voltage to the gate of Mp 1 during normal operation and is shut off during an OVST test, thereby turning off switch Mp 1 . The switch Mp 1 during OVST testing will be off and serves to eliminate the current path to source node Vdd and protects the remaining circuitry (devices Mn 1 and Mn 3 ) from the high voltage applied to node Vgp during OVST. [0009] While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

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